1. Field of the Invention
This invention relates to integrated circuits and, more particularly, to techniques for reducing high voltage stress on the transistors of a high-voltage detector circuit which distinguishes, for example, between 13 volts and 6 volts.
2. Prior Art
Voltage stress on the gate oxide of an integrated-circuit transistor produces long-term degradation of the transistor. It has been found that an electric field in the range of 7 to 10 Megavolts per centimeter across a gate-oxide causes charge to be injected into the gate oxide. This injected charge causes long term degradation of the transistor, such as, for example, threshold voltage variations, variations in mobility, etc.
An example of a circuit in which the gate oxide of a transistor is stressed by high voltage is a detector circuit which is used to detect the presence of a 13 volt programming voltage used for programming an array of anti-fuse memory circuits. The detector circuit can have 13 volts across the gate oxide of a detector transistor. For a gate oxide thickness of 165 Angstroms and a voltage of 13 volts, an electric field of 7.88 MegaV/cm is generated between the top of the gate and the substrate of the transistor. An electric field of this magnitude is within the range where long-term degradation occurs.
FIG. 1 is a circuit diagram 100 of a prior art high voltage detection circuit 100 for detecting the presence of a 13 volt programming voltage or a 6 volt supply voltage. This circuit is designed to discriminate between a 13 volt signal or a 6 volt signal provided at an input terminal 102. The input terminal 102 is connected to the drain and source terminals of NMOS transistor 104. A substrate terminal for NMOS transistor 104 is connected to a ground reference voltage. The source terminal of the transistor 104 is connected to the source and substrate terminals of a PMOS transistor 106. The gate terminal of the PMOS transistor 106 is connected to VCC and to the gate terminal and the drain terminal of another NMOS transistor 108. The source terminal of PMOS transistor 106 is connected to the source terminal of NMOS transistor 108. The drain terminal of the PMOS transistor 106 is connected to a drain terminal of a NMOS bleeder transistor 110 and to an output terminal 112. The source terminal of the NMOS bleeder transistor 110 is connected to a ground reference voltage. The gate terminal of the NMOS bleeder transistor 110 is connected to VCC. The NMOS bleeder transistor 110 provides a fixed resistance to ground for draining charge on the output terminal 112 to ground when 6 volts appears at the input terminal 102. In operation, a 13 volt signal on terminal 102 causes a logical high voltage to appear on output terminal 112. A 6 volt signal on terminal 102 causes a logical low voltage to appear on output terminal 112.
A problem with the voltage detection circuit 100 of FIG. 1 is that 13 volts can appear across the gate oxide of NMOS transistor 104 between the gate terminal and the substrate terminal. The thickness of the gate oxide of transistor 104 can range between 165 to 185 Angstroms. With 13 v and 165 Angstroms, the field across the gate oxide of transistor 104 is 7.88 MegaV/cm between the top of the gate and substrate. An electric field in the range of 7 to 10 MegaVolts per centimeter causes charges to be injected into the gate oxide resulting in a long term degradation of the transistor.
Consequently, a need exists for a voltage detector circuit which can discriminate between a 13 v programming voltage and a 6 v voltage without creating a field across the gate oxide of a sensing transistor in excess of 7.0 MegaV/cm.